An expression that converts the value of a subexpression from one type to the designated type of the type conversion.
Complete description: Language Reference Manual §7.3.5.
type_mark ( expression )
VHDL is a strongly typed language. This causes that objects of even closely related types need a conversion, if they are supposed to be used together.
The result of the conversion is an object, which type is the same as the type specified by the type_mark (Example 1). The type of the operand (the expression) must be known independently from the context. Moreover, the operand cannot be an aggregate, an allocator, the literal null, or a string literal.
A type conversion is restricted to closely related types, i.e. must conform to the following rules::
All abstract numeric types (integers and floating point numbers) are closely related types. When a floating-point number is converted into an integer, the result is rounded to the nearest integer.
Two arrays are closely related types if:
Both arrays have the same dimensions,
their elements are of the same type,
for each range, the index types are the same or closely related.
No other types are closely related.
If the type_mark indicates an unrestricted array type, then after the conversion the range boundaries are moved from the operand. If the type_mark indicates a restricted array type, then the range boundaries of the array are described based on this type. After the conversion, the elements values of the array are equal to the elements values before the conversion.
Example 1
This assignment contains two type conversions: first Param_Calc is converted to a real value in order to multiply it with a universal real. Then the result of the multiplication is converted back to an integer and assigned to Data_Calc.
No conversion is needed between any type or subtype defined on its basis.
Two arrays may be closely related even if corresponding index positions have different directions.